DSPW=Val_0x0, INTM=Val_0x0, SWR=Val_0x0
Bus Mode Register
| SWR | Software Reset When this bit is set, the MAC and the DMA controller reset the logic and all internal registers of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is complete in all ETH module clock domains. Before reprogramming any ETH module register, a value of zero should be read in this bit. This bit must be read at least 4 CLK_CSR cycles after it is written to 1. Note: The reset operation is complete only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0 (Val_0x0): Software reset is disabled 1 (Val_0x1): Software reset is enabled |
| DSPW | Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted. When this bit is set to 1, the descriptor writes are non-posted only when IOC (Interrupt on completion) is set in last descriptor, otherwise the descriptor writes are always posted. 0 (Val_0x0): Descriptor posted write is disabled 1 (Val_0x1): Descriptor posted write is enabled |
| INTM | Interrupt Mode This field defines the interrupt mode of the ETH module and changes the behavior of the ETH_SBD_IRQ signal. It also changes the behavior of the ETH_DMA_CH0_STATUS[RI] and ETH_DMA_CH0_STATUS[TI] bits. 0 (Val_0x0): ETH_SBD_IRQ is asserted when corresponding interrupts are enabled, and cleared only when software clears the corresponding RI/TI status bits. 1 (Val_0x1): ETH_SBD_IRQ is not asserted on TX/RX packet transfer completion event. 2 (Val_0x2): ETH_SBD_IRQ is not asserted on TX/RX packet transfer completion event. |